Level shifting circuits can shift an input signal, that transitions between a first voltage range, into an output signal that transitions between a second voltage range, that can be greater or smaller than the first voltage range. Level shifting operations are typically utilized to allow one signal, generated in one voltage domain (i.e., range), to drive circuits operating in another voltage domain. For applications in which level shifters are included in timing signal paths, ensuring predictable signal delays can present design challenges.
To better understand various features of the disclosed embodiments, a conventional level shifting circuit will now be described.
Referring now to FIG. 9, a conventional level shifting circuit is shown in a schematic diagram and designated by the general reference character 900. A level shifting circuit 900 can include a low voltage input section 902, a level shifting stage 904, and a high voltage output stage 906. In response to a low-to-high transition (VSS to VDD_LO) of an input signal IN received by low voltage input section 902, conventional level shifting circuit 900 can generate an output signal OUT that transitions from low-to-high (VSS to VDD_HI). Conversely, in response to a high-to-low transition (VDD_LO to VSS) of input signal IN, conventional level shifting circuit 900 can generate an output signal OUT that transitions from high-to-low (VDD_HI to VSS).
However, in the conventional level shifting circuit shown, different types of input transitions have different circuit delay components. In particular, a conventional low-to-high response can be described as introducing a rise delay (Delay_HI) expressed as follows:Delay—HI=tf1+tr2+tfa+trd+tf6+tr7where tf1 is a fall delay introduced by inverter 1, tr2 is a rise time introduced by inverter 2, tfa is the delay introduced by n-channel transistor “a” driving the gate of p-channel transistor “d” low enough to turn on transistor “d”, trd is the delay introduced by transistor “d” driving the input of inverter 6 high, tf6 is a fall delay introduced by inverter 6, and tr7 is a rise time introduced by inverter 7.
In a similar fashion, a high-to-low response can be described as introducing a fall delay (Delay_LO) expressed as follows:Delay—LO=tr3+tf4+tr5+tfb+tr6+tf7where tr3 is a rise delay introduced by inverter 3, tf4 is a fall delay introduced by inverter 4, tr5 is a rise time introduced by inverter 5, tfb is the delay introduced by n-channel transistor “b” driving the input of inverter 6 low, tr6 is a rise delay introduced by inverter 6, and tf7 is a fall time introduced by inverter 7.
While a conventional approach can attempt to tune the above delays (for example, by sizing transistors) to try to create equal values for Delay_HI and Delay_LO, such a balance is very difficult to achieve over wide range of operating conditions and/or process variations.
A reference to the above expressions shows that value Delay_HI includes components tfa (introduced by n-channel device a) and trd (introduced by p-channel device d). In contrast, the value Delay_LO only includes component tfb (introduced by n-channel device b). These delay components of the level shifting stage 904 can vary as power supply voltage levels vary. Further, changes in fall components (e.g., tfa and tfb) of level shifting stage 904 due to different power supply voltage levels do not track corresponding changes in rise components (e.g., trd). Further, these delays can further vary due to manufacturing process variations and/or operating temperature.
All of the above make it difficult to achieve balanced delay times (rise and fall) utilizing conventional techniques.